Computer processing systems use several kinds of memory structures based on technologies such as dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), etc. These memory structures are conventionally designed as memory arrays comprising memory cells or bit cells. Specialized write circuitry may be required for writing data to be stored in the bit cells of the memory arrays to suit individual needs of the memory arrays.
In one example, for an SRAM array comprising an array of bit cells, true and complement write bitlines may be used for writing the bit cells. A local write driver circuit may be employed for effectively driving the write bitlines in order to write the bit cells during a write operation. However, since reducing power consumption is an important consideration in many processing systems, the write driver circuitry may also be configured to float the write bitlines when a write operation is not being performed, in order to reduce leakage power.
Conventional write driver circuits may use tri-state drivers gated by an enable clock in order to achieve the above functions of driving or floating true and complement versions of the write bitlines. However, such conventional write drivers may be prone to several problems. Controlling setup and hold times for the write bit lines driven by tri-state drivers tends may be difficult. This is because race conditions may arise during the operation of the tri-state drivers. A back-end self-timed race condition pertains to a requirement for data driven on the true and complement write bitlines to hold past a falling edge of the write clock used for the write operation. This back-end self-timed race condition may arise in the case of edge-triggered designs as well as transparent latch designs. In the case of an edge-triggered interface design, where the data inputs return to zero (RTZ) during a low phase of a system clock, these data inputs need to hold past the falling edge of the write clock. If the data inputs do not hold past the falling edge of the write clock, a critical internal race margin may be violated and incorrect values may be written to the bit cells. Further, the data inputs need to meet setup margins with relation to the write clock in order to prevent glitches on the write bitlines. Failing to meet the setup margins may lead to errors and loss of dynamic power resulting from unnecessary switching of static write bitlines.
Further, the conventional tri-state drivers use stacked transistors (e.g., n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) gates) for their operation in driving and floating the bitlines. These stacked structures affect writability at low supply voltages and require larger sizing for required drive strength, thus incurring costs in terms of area and dynamic power.
Another problem in conventional write driver circuits relates to voltage scaling. The write drivers may need to translate signals from one voltage domain to another. For example, the memory array may belong to a first voltage domain, which may be a low voltage domain to reduce power consumption of the memory array. The true and complement write bitlines may carry data supplied from a second voltage domain, which may be a higher voltage domain in order to meet requirements for writeability of bit cells. For example, the minimum voltage required to be able to write SRAM bit cells may be high, which would require driving a higher voltage on the write bitlines.
Utilizing a single level shifter in write bitline drivers for shifting the true and complement write bitlines from the second voltage domain to the first voltage domain may be problematic. When no active write is performed, i.e., when the true and complement write bitlines are in a low phase or when both carry a zero binary value, the single level shifter may drive the write driver circuit into an unknown state, which may be difficult to recover from.
Conventional write bitline drivers which include a single level shifter may accept non-RTZ data input signals. The output of the level shifter output is then merged with a level shifted write clock at the write bitline driver. For such conventional designs, the level shifter must provide a balanced delay for both rising and falling data inputs, which poses significant design challenges.
Accordingly, there is a need to avoid the aforementioned drawbacks associated with conventional implementations of level shifters pertaining, for example, to memory array write bitline drivers.